Embedded storage on integrated circuits requires a lot of space. Now a more economical architecture is promising cheaper and more energy-efficient devices in future.
Integrated circuits (chips) play a central role in nearly all electronic devices. Along with the “logic” for the instruction processing, on-chip storage takes up the lion’s share of the silicon content. On average, it can currently hold several hundred megabytes and occupies up to 75 percent of the chip’s surface. Megatrends such as machine learning, 5G, augmented reality or the internet of things (IOT) will further intensify this imbalance in future.
For this reason, manufacturers have long been on the search for possible ways of reducing the footprint of storage, ultimately making devices smaller, cheaper and more effective. Researchers at the Bar-Ilan University (BIU) in Israel and the EPFL in Lausanne appear to have taken a significant step towards achieving this with a new design.
At first sight, their solution seems quite obvious: simply reducing the number of transistors. To do this, the researchers changed the usual arrangement of the transistors and used shortcuts. Their GC-eDRAM (Gain Cell embedded DRAM) requires only two or three transistors to store one bit, instead of the six or eight in conventional SRAMs. This creates space for more storage or other components and reduces the energy consumption.
eDRAMS are actually already on the market, but are rarely used in the semiconductor industry as they are not compatible with current processes of chip production. The GC-eDRAM, meanwhile, can be integrated into the existing standard manufacturing process. Tests with semiconductor manufacturers on chips between 16 nanometers and 180 nanometers and with a storage capacity of up to a megabyte have already been completed successfully.
This chip storage solution reached the top three in a Swiss venture program with 330 entrants. The technology is currently being commercialized by the RAAAM company.