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Architectural Exploration for AI and Machine Learning with the flexibility of RISC-V

NOV
09
2020
09. NOV 2020

Lecture Embedded Forum > Tools & Software

12:20-12:40 h | Virtual

A modem SoC project is a combination of hardware and processor resources with the software application that together provide an optimal solution for the targeted end market use case. The AI and machine learning algorithms have been developed and perfected in cloud-based platforms and training datasets base on significant real-world data. To further enhance the performance for applications in edge devices the use of dedicated hardware can be explored to fine tune the optimum configuration of many core processors. RISC-V offers not just the flexibility to configure each node to match the performance requirements but can also support custom instructions and extensions. Custom instructions can help address the needs of the target applications by accelerating common routines or with dedicated core to core lightweight communication in many core arrays. This talk with cover the migration of cloud-based algorithms to dedicated hardware acceleration with the design flexibility RISC-V now offers system designs for SoC, FPGA and chiplet designs.

Subjects: Embedded systems

Speaker: Simon Davidmann (Imperas)

Type: Lecture

Speech: English

A modem SoC project is a combination of hardware and processor resources with the software application that together provide an optimal solution for the targeted end market use case. The AI and machine learning algorithms have been developed and perfected in cloud-based platforms and training datasets base on significant real-world data. To further enhance the performance for applications in edge devices the use of dedicated hardware can be explored to fine tune the optimum configuration of many core processors. RISC-V offers not just the flexibility to configure each node to match the performance requirements but can also support custom instructions and extensions. Custom instructions can help address the needs of the target applications by accelerating common routines or with dedicated core to core lightweight communication in many core arrays. This talk with cover the migration of cloud-based algorithms to dedicated hardware acceleration with the design flexibility RISC-V now offers system designs for SoC, FPGA and chiplet designs.

Speaker,
Imperas

Simon Davidmann

Simon Davidmann

Imperas

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Informations

Speaker,
Imperas

Simon Davidmann
Simon Davidmann
CEO

Location

Eingang
Nord-West
ICM
Eingang
Nord
Eingang
West
Atrium
Eingang
Nord-Ost
Eingang
Ost
Conference
Center Nord
Freigelände
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C4
C5
C6
B0
B1
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B6
A1
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